1. Field of the Invention
This invention relates to a reference circuit for a variable impedance output buffer and, more particularly, to a binary weighted reference circuit producing a variable impedance output buffer.
2. Description of Prior Art
To maximize the transfer of electrical power, a driver connected to a transmission line needs to have its output impedance matched to the impedance of the transmission line. To accomplish this matching, variable impedance output buffers have been used to vary the impedance of an output buffer to the impedance of the transmission line.
A prior art variable impedance resistor is shown in FIG. 1. The resistance across terminals A and B is a digitally controlled CMOS resistor having a plurality of transistors MP0, MP1, MP2, . . . MPN. The transistors MP0, MP1, MP2, . . . MPN are binary weighted transistors with the first transistor MP0 having a width of 2.sup.0 times a reference width w.sub.ref, the second transistor MP1 having a width 2.sup.1 times the reference width w.sub.ref, the third transistor MP2 having a width 2.sup.2 times the reference width w.sub.ref, etc. The different widths in transistors MPO, MP1, MP2, . . . MPN produce different resistances across the drain and sources of the transistors. Thus, the resistance across terminals A and B can be varied by varying the conductance of transistors MP0, MP1, MP2, . . . MPN.
An input signal inverted with inverter INV is supplied to one input of NAND gates N0, N1, N2, . . . NN. The other input to each NAND gate is connected to a respective line of a control bus. The outputs of the NAND gates N0, N1, N2, . . . NN are inverted and are respectively supplied to the gates of transistors MPO, MP1, MP2, . . . MPN. For instance, the first bit 0 of the control bus is connected to the first NAND gate N0, which has its output inverted and connected to the gate of the first transistor MP0.
The variable resistance shown in FIG. 1 may be used in a circuit shown in FIG. 2. In this circuit, the potential V.sub.MID between resistances R2 and R3 is passed through a low pass filter 2 and then supplied to one input of a comparator 6. The other input to the comparator 6 is supplied with a potential V.sub.LHALF after passing through a low pass filter 4. Based upon a comparison of V.sub.MID to V.sub.LHALF, the comparator 6 produces an up/down signal U/D which is supplied to a D flip-flop 8. The D flip-flop 8 is clocked by a ring oscillator 10 and supplies its Q output to an up/down counter 12. The output from the up/down counter 12 is then supplied to a transistor array 14, such as the one depicted in FIG. 1. Thus, the circuit shown in FIG. 2 adjusts the impedance across terminals A and B until the potential V.sub.HALF matches the potential V.sub.MID.
Because not all transmission lines have the same impedance, an external reference pin is added to an integrated circuit 14 of the output buffer. This reference pin is connected to a supply voltage V.sub.DD via a resistor R.sub.1 having a resistance equal to the impedance of the transmission line. The other side of the resistor from the supply voltage V.sub.DD is connected to an on-chip reference circuit that has its impedance varied to match the impedance of the external resistor R.sub.l.
Because the reference circuit is fabricated on the same chip as the output driver, there is a need in the prior art for smaller reference circuits and for matched circuit layouts.